Veröffentlichungen
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K. Harbich: "Fehleremulation für Automotive-Applikationen",
Design & Verification, September 2004, publish-industry Verlag, München 2004
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K. Harbich: "A Timing-Driven RTL-based Design Flow for Multi-FPGA Rapid Prototyping",
Fortschritt-Berichte VDI, Reihe 20, Nr. 367, Reutlingen, 2002
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K. Harbich, E. Barke: "PuMA++: From Behavioral Specification to
Multi-FPGA-Prototype", FPL '01: 11th International Conference on Field
Programmable Logic and Applications, Belfast, 2001, pp. 133-141
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K. Harbich, O. Bringmann, E. Barke: "PuMA++: A Fully Automatic Path
from Specification to Multi-FPGA-Prototype", FPGA '01: International Conference
on Field Programmable Gate Arrays, Monterey, 2001, Poster
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K. Harbich: "PuMA++: Ein universelles Abbildungssystem für
Multi-FPGA Rapid-Prototyping-Systeme", ITG Workshop Mikroelektronik für
die Informationstechnik, Darmstadt, November 2000, pp. 231-234
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K. Harbich, J. Abke, E. Barke: "PuMA: An Optimised Partitioning and Mapping
Environment for Rapid Prototyping of Structural RT-level Circuit Descriptions",
DATE 2000: 3rd Design Automation and Test in Europe, Paris, 2000, University
Booth, Tool-Demonstration
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K. Harbich: "Delay Optimized Hardware Implementation of Structural RT-level
Circuit Descriptions into Heterogeneous SRAM-based FPGA-Arrays", DAC '99:
36th Design Automation Conference, New Orleans, 1999, Ph.D. Forum (Poster)
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K. Harbich, J. Stohmann, L. Schwoerer, E. Barke: "A Case Study: Logic Emulation
- Pitfalls and Solutions", RSP '99: 10th IEEE Workshop on Rapid System
Prototyping, Clearwater, FL, 1999, pp.160-163
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J. Stohmann, K. Harbich, M. Olbrich, E. Barke: "An Optimized Design Flow
for Fast FPGA-Based Rapid Prototyping ", FPL '98: 8th International Workshop
on Field Programmable Logic and Applications, Tallin, 1998, pp.79-88
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K. Harbich, H. Hoffmann, E. Barke: "A New Hierarchical Graph Model for
Multiple FPGA Partitioning", WDTA '98: IEEE Workshop on Design, Test and
Application, Dubrovnik, 1998, pp. 101-104
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K.Harbich, D. Behrens: "Hierarchische Partitionierung von integrierten
Digitalen Schaltungen für homogene FPGA-Arrays", Mikroelektronik '97,
München, 1997, S. 67-74, Session B2: Designmethods and Tools [Tagungsband]
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D. Behrens, K. Harbich, E. Barke: "Circuit Partitioning Using High-Level
Design Information", IDPT '96: 2nd World Conference on Integrated Design
& Process Technology, Austin, Texas, 1996, S. 256-266 [Tagungsband]
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D. Behrens, K. Harbich, E. Barke: "Hierarchical Partitioning", ICCAD '96:
International Conference on Computer Aided Design, San Jose, 1996, pp.
470-477 [Tagungsband]
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J. Stohmann, K. Harbich, D. Behrens: "Ein neuer optimierter Designflow
für Rapid-Prototyping-Systeme", 3. SICAN Herbstagung, Hannover, 1996,
S. 15-18 [Tagungsband]
Wenn Sie mir schreiben wollen oder mehr Informationen benötigen...
Letzte Änderung: 13.10.2004